Verilog reg assignment?

2 Answers 2

Are reg types only assigned in always@ block?

No, reg types can be assigned in always blocks and initial blocks (plus task and function but I'll skip them in the scope of this question)

For your fourBitCounter , the reg[3:0] counter declared in the initial block creates a local variable also called counter that is only accessible within the scope of the block it was created in. You need to remove the reg[3:0] in the initial block so that the assignment get applied the the intended counter . But it will still not work because you declared counter as an inferred wire type and always / initial blocks cannot assign wires.

counter was declared as an output of a 4-bit inferred wire ( output [3:0] counter is synonyms to output wire [3:0] counter ). Since counter is assigned in an always block and initial block it needs to be a reg type. Therefore it should be declared as output reg [3:0] counter .

Also, you declared clk as in input and as a local wire, it cannot be both. Ports can be accessed locally, there is no reason to re-declare them as local nets.

FYI: for a 4-bit value, 15+1 equals 0 because there is nothing to store the MSB.

module fourBitCounter ( input clk, output reg [3:0] counter // 'output reg', not 'output' ); //wire clk; // do not do this, clk is an input initial begin counter = 4'b1; // no 'reg' here end always @(posedge clk) begin if(counter > 15) // this will never evaluate as true with counter declared as 4-bit counter 

For Verilog, assign statements can only be applied on net types (e.g. wire ). This is legal:

module test ( output LED0 ); // LED0 is an inferred wire assign LED0 = 1'b1; endmodule 

This is illegal:

module test ( output reg LED0 ); // Explicit reg assign LED0 = 1'b1; // illegal, assign on a reg endmodule